Archive for September, 2009

ASIC_timing updated 10/6

Here’s the draft for the ‘Electronics and Transmission Line Readout’ poster for the DOE site visit next Wednesday. Please send me any comments. (updated 9/18)




Hey All,

The “AC test module” is now divided into two parts.  Both parts are completely routed and ready for submission after the pinout check and HyperLynx PI simulation get performed.

The first part is the $$$ analog stud bonding board.  Here’s a layout pic of the analog board’s TOP and bottom layer.  Here’s a copy of the analog board schematic.  The dimension of the analog board is 1.89009 inches by 2.150 inches.
The second part is the dirt cheap digital board. Here’s the layout pic and a copy of the digital board schematics.  The dimension of the digital board is 4.702 inches by 2.9275 inches

Here’s the remaining tasklist:

1) Simulate 4x different TX-lines (Larry – waiting for HyperLynx PI license)

2) Double check my ps_TDC_01 ASIC pinout (Eric)

3) Submit boards for fabrication(Waiting for items#1-2 and funding to come to Hawaii)


Hey All,

Here’s a link to the updated schematics.  I am also done with the entire circuit board layout expect for the 4x TX-line.  I have also added a screen capture of the top layer layout.  Since this prototype board production is going to a lot of $$$, I am going to require the following task list to be done before I submit this layout for fabrication.

1) Get RF dielectric information properties from fabrication house (Larry)

2) Simulate 4x different TX-lines (Larry – waiting for item#1)

3) Double check my ps_TDC_01 ASIC pinout (Eric)

4) A very detailed design review of my schematics (Gary/Jean-Francois)

5) Submit board into layout (Waiting for items#1-4 and funding to come to Hawaii)


A second look at comparator response. Simulated using comparator as implemented on chip.  The output was loaded with .5-1 pF cap to be realistic. Seems comparator will work for all of linear ramp range.
comp response


Here’s a draft of the PS_TDC_01_eval schematics.  Speak up if you see something wrong with it.


Ramp buffer schematic/simulation.  Shows dynamic output range of ramp buffer.


Comparator response time & variation – thinking about the next chip
ADC comparator

in addition, an old plot: post layout response of implemented comparator

comp post layout