Archive for January, 2010

Here are the testing conditions:

– “CEXT” tied to VDD

– “VPED” tied to GND

– TRIG(4 downto 0) <= “00000”;

– AD(4 downto 0) <= “11111”;

-2G CLK = 40 MHz

– IBIAS_CP <= a free parameter which was scaned;

– IBIAS_RP <= 1.2V;

– V_POL <= 0.4V;

Here’s a schematic drawing of the Wilk. ADC Circuit.  With this configuration I am always resampling every sample w.r.t WR_CLK duty cycle, which will set the positive input of the comparator = GND.  By tying CEXT to VDD, the negative input of the comparator = VDD.  Thus, the comparator should ALWAYS be off.  With the comparator ALWAYS off, then the ADC counter should NEVER count.

After I strobe the ADC_CLR line to reset the WILK Counter (….and yes, I have confirmed that if I set ADC_CLR high always that the ADC bus is always zero), then I readout each Wilk. Register and see random ADC counts over the entire range.  By slowing down the RD_CLK to a very slow rate and observing the ADC bits on an O-scope, I can observe that the bits are still changing in the middle of the readout due to the fact that the counter is still counting.

Note: that the CEXT node doesn’t seem to be broke since we are measuring a 165 Ohms to GND, which is to be expected.

Note: I get the same results for all values of IBIAS_CP across the entire voltage range of IBIAS_CP.

Here is what I suspect is going wrong with the ASIC:

– due to the “broken pad buffer” that we are unable to couple an analog ramp signal into the ASIC

-the comparator circuit in this ASIC is “broken” and just banging away like no ones business

In either case, we will never be able to digitize waveforms with this version of the psTDC ASIC since the Wilk. ADC circuit is not functional.

-Larry

Here’s what I am currently seeing for the ADC data with running in a 8-bit ADC mode.

-Larry

Here are two waveform captures of the latency between the WR_CLK to VDL_OUT edges with MCK_RTN tied to VCN and MCK_RTN floating.  I see no difference.  Both have a delay of ~50 ns with VCN = 1.2V and VCP = 0.0V.

Good news: if we don’t have them no bump bond MCK_RTN, then we should be able to use the existing AC cards.

Bad news: I am getting the roughly the same sampling speed as Eric. (256/50ns) = ~5 GSa/s……..the same sampling speed as Hawaii’s BLAB1 ASIC, lol.

-Larry

Here’s the TOK timing.  The chipscope time base is 10 ns (based on a 100 MHz reference CLK).  There is about 200 ns delay between the rising_edge of RD_CLK to the output of the flip-flop.

-Larry

For the Wilk_CLK testing, Here’s the results.  Repeats the delta voltage versus Wilk. Clock frequency.  The legend decoding is

CK_CV_01 = CK_CV (not the test structure) for Hawaii’s DC card #1

CK_CV_02 = CK_CV (not the test structure) for Hawaii’s DC card #2

TEST_2G_01 = TEST_2G for Hawaii’s DC card #1

TEST_2G_02 = TEST_2G for Hawaii’s DC card #2

The results looks very good for the test structure.  Actually, better than what was measured previously.  I contribute the better performance due to the fact that all the VDD and GND are connected for Hawaii’s wired-board DC testing card.

However, the Wilk. Clock connected to the sampling array is much slower and “craps” out at a lower voltage.  Here were a list of question that Gary and I were wondering:

1) Is the output pad for TEST_2G the same as CK_CV?

2) Has a simulation been done to show that the Wilk. clock can drive the capacitance loading (including parastics) for all the digital counters?

======================================================

A much bigger concern on my side is “VDL_OUT”.  We are inserting a 40 MHz clock into the WCLK digital_IO and are not seeing anything change on VDL_OUT for the entire delta V range (VCP & VCN).  Have you guys tested this part on your DC testing card?  If I can’t see a copy of the clock on VDL_OUT, then we are mostly not sampling, which mean I am stuck.  We can discuss this more in detail in tomorrow’s meeting.

-Larry