Archive for February, 2011

0/. Howtos:

Do a resistance extracted simulation in Cadence: Howto Cadence Parasitic R
Do a board simulation in from Layout to Hyperlynx: Howto Hyperlynx

1/. Simulation of  the input lines in Cadence with extracted resistances and capacitances:

The way Cadence calculate the resistance is the following: the user set a DC bias voltage on every input of the structure to simulate. From what i understand the current generated by the DC level is use to calculate the resistance of each node.

However by definition no DC current can flow in the input line. The resisatnce value generated for the input line is therefore not matching the reality at all:

Vin Totals: R ~2.181m C =1.506p
Vbias Totals: R = NS C = 10.79p

The simulation of the input line even with parasitic included R & C are therefore non-conclusive.
Next step: Wait for the flip-chip and quad-flat mezzanine board.

2/. Simulation of the board in Hyperlynx

By construction the net gnd is impossible to simulate and to add component onto. I cannot simulate the board the way i want to. A plot of the input line is shown in the tutorial, without the decoupling capacitance to the ground the simulation is clearly useless.
Next step: wait for the mezzanine board on which Mircea designed different input lines.

3/. DLL locking range issue

Went back to simulate the DLL at different frequencies than 40MHz. It does lock. The two impacting parameters are: The polarization current and the capacitance.
From Eric’s test the DLL only work at 40MHz, not 20, not 60, …very strange
Even more strange this is not affected at all by the polarizating current or the value of the capacitance…
No clues for now

4/. Using the method of David Mc Ginnis to calculate the field in the anode

I am stuck with a no flux current on my metal sheet: rapport pour David

5/. Trying to plug the board on my laptop

I am have an issue with the USB driver (my laptop is 64 bit). If anyone in Hawaii has the Cypress driver for 64 bit i would appreciate a lot. I spend quite some time trying to get the board to talk with my computer with no luck.

Hervé Grabas

Timing resolution vs Signal to Noise/ Analog Bandwidth and Sampling Frequency

Presentation

Jean-François Genat

Klaus is interested with our electronics, talking with him his need would be:

” I have not made a clear plan what to measure but it is clear that one wants to see how the electronics behaves in real environment. I guess one question would be:
1.) trigger and trigger jitter
2.) can the pulse-height be extracted and how does it compare with other electronics
3.) how good is the timing
Currently I use a sample averager card which runs with 1GHz. This works quite well but the number of points which can get fit is quite low. So I look for an alternative.
The pulses wich I can get: Everything between 400ps to 5-6ns with rise time between 46ps and about 800-900ps.
Typically I setup detectors and use parasitically airscattered light (either x-rays or laser). ”

I guess the remaining questions are
1/. What is the rate
2/. What is the number of channel needed
3/. What is the height of the signal across 50 ohms
4/. Is the trigger internal or external

Hervé Grabas