Archive for April, 2011

Resistivity of metal layers and vias IBM0.13

To be noticed:

1/. Very high resistivity of CA via!!
2/. Via resistivity higher than CA ~ cst.
3/. Gain a factor 10 by going higher than MQ/MG!!

Hervé Grabas

PSEC3_BW (pdf)

Eric

UC_champ_testing (pdf) ….in progress

eric

Linearity & noise of the digital conversion for Psec4 (red) vs Psec3(blue)

Full ADC cell simulator

Accumulated design knowledge allow today for a: low-noise/high-linearity ADC cell (sampling+comparator). Using Virtual ADC and Virtual White Noise Source (Verilog-A) in simulation allows fast/accurate/extensive ADC simulation (new!).

Hervé Grabas

20110413_psec3meztests