Archive for July, 2011


Code documentation v1-1 (pdf)

Includes VHDL code for multi-threshold, leading edge, and constant fraction timing discriminators; baseline average, standard deviation, and significance calculators; pulse integral, average height, peak height, rising and falling times, and full width at half max calculators, along with appropriate simulations and a few remarks about how to use and manipulate the code.

As of August 1 2011, the code simulated in the above document has been successfully uploaded into a Cyclone IV development board, and the results of a number of simulations executed on said board are recorded in the following document:

Chip simulations (pdf)

The raw code will be uploaded to the psec website later this week (week of Aug. 1), as some effort still needs to be put into cleaning up the code and converting it into a more palatable modular form. To give a taste for what the code looks like at this point, here is a text version of the multi-threshold and linear-fit timing discriminators:

example code (text)