Archive for November, 2011

PLL_Timing_22_11_11_JFG

revision 2 schematics

Modifications from first revision:

1) addition of 10K current return resistors

2) One optionally-installed 90º SMA connector on channel 6 of each PSEC-4. (allows for in-situ timing calibrations via sine input/strip signal injection/etc testing.)

+

pcb layout progress (board dimensions ~2.3 x 8.66 sq inch [5.8 x 23.0 cm*cm])

Eric

PSEC4power

Calculations

1)Eric’s tests for the PSEC  as  Power(frequency)

2)My calculations for power consumption for the PSEC4- Analog board.

I’m still in training today will not be able to make the meeting.
-Craig

Digital Card Requirements and Specs